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drm/amdgpu: enable cp_fw_write_wait for navy_flounder
author
Jiansong Chen
<Jiansong.Chen@amd.com>
Wed, 24 Jun 2020 04:47:54 +0000
(12:47 +0800)
committer
Alex Deucher
<alexander.deucher@amd.com>
Wed, 15 Jul 2020 16:47:09 +0000
(12:47 -0400)
It's the same with sienna_cichlid, cp fw for navy_flounder
can support WAIT_REG_MEM packet.
Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
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diff --git
a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 3799185430dfd552e38d4da9fbfd3a13bed38087..61e89247faf3bcd7ae98293714a93cf5a372a4f2 100644
(file)
--- a/
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@
-3538,6
+3538,7
@@
static void gfx_v10_0_check_fw_write_wait(struct amdgpu_device *adev)
adev->gfx.cp_fw_write_wait = true;
break;
case CHIP_SIENNA_CICHLID:
+ case CHIP_NAVY_FLOUNDER:
adev->gfx.cp_fw_write_wait = true;
break;
default: