drm/amdgpu: enable fgcg for soc21

Enable Fine Grained Clock Gating on soc21 asics.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/soc21.c b/drivers/gpu/drm/amd/amdgpu/soc21.c
index dc200d11fcca6fdf538043431edf1e4a7b26c880..d738635ecf1d1b62e7ce2e47f3c47fe47d1c2280 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/soc21.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc21.c
@@ -481,7 +481,8 @@ static int soc21_common_early_init(void *handle)
        switch (adev->ip_versions[GC_HWIP][0]) {
        case IP_VERSION(11, 0, 0):
                adev->cg_flags = AMD_CG_SUPPORT_GFX_CGCG |
-                       AMD_CG_SUPPORT_GFX_CGLS;
+                       AMD_CG_SUPPORT_GFX_CGLS |
+                       AMD_CG_SUPPORT_REPEATER_FGCG;
                adev->pg_flags = AMD_PG_SUPPORT_ATHUB |
                        AMD_PG_SUPPORT_MMHUB;
                adev->external_rev_id = adev->rev_id + 0x1; // TODO: need update