ARM: dts: qcom: ipq4019: align dmas in SPI/UART with DT schema

The DT schema expects dma channels in tx-rx order.  No functional
change.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220405063451.12011-4-krzysztof.kozlowski@linaro.org

diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi
index a9d0566a319092796937760fabe97ef95ae65c79..1f6c4ab7f37ef999cb4b1d5e7e0f126db86e4844 100644 (file)
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -253,8 +253,8 @@ blsp1_spi1: spi@78b5000 { /* BLSP1 QUP1 */
                        clock-names = "core", "iface";
                        #address-cells = <1>;
                        #size-cells = <0>;
-                       dmas = <&blsp_dma 5>, <&blsp_dma 4>;
-                       dma-names = "rx", "tx";
+                       dmas = <&blsp_dma 4>, <&blsp_dma 5>;
+                       dma-names = "tx", "rx";
                        status = "disabled";
                };
 
@@ -267,8 +267,8 @@ blsp1_spi2: spi@78b6000 { /* BLSP1 QUP2 */
                        clock-names = "core", "iface";
                        #address-cells = <1>;
                        #size-cells = <0>;
-                       dmas = <&blsp_dma 7>, <&blsp_dma 6>;
-                       dma-names = "rx", "tx";
+                       dmas = <&blsp_dma 6>, <&blsp_dma 7>;
+                       dma-names = "tx", "rx";
                        status = "disabled";
                };
 
@@ -281,8 +281,8 @@ blsp1_i2c3: i2c@78b7000 { /* BLSP1 QUP3 */
                        clock-names = "iface", "core";
                        #address-cells = <1>;
                        #size-cells = <0>;
-                       dmas = <&blsp_dma 9>, <&blsp_dma 8>;
-                       dma-names = "rx", "tx";
+                       dmas = <&blsp_dma 8>, <&blsp_dma 9>;
+                       dma-names = "tx", "rx";
                        status = "disabled";
                };
 
@@ -295,8 +295,8 @@ blsp1_i2c4: i2c@78b8000 { /* BLSP1 QUP4 */
                        clock-names = "iface", "core";
                        #address-cells = <1>;
                        #size-cells = <0>;
-                       dmas = <&blsp_dma 11>, <&blsp_dma 10>;
-                       dma-names = "rx", "tx";
+                       dmas = <&blsp_dma 10>, <&blsp_dma 11>;
+                       dma-names = "tx", "rx";
                        status = "disabled";
                };
 
@@ -382,8 +382,8 @@ blsp1_uart1: serial@78af000 {
                        clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
                                <&gcc GCC_BLSP1_AHB_CLK>;
                        clock-names = "core", "iface";
-                       dmas = <&blsp_dma 1>, <&blsp_dma 0>;
-                       dma-names = "rx", "tx";
+                       dmas = <&blsp_dma 0>, <&blsp_dma 1>;
+                       dma-names = "tx", "rx";
                };
 
                blsp1_uart2: serial@78b0000 {
@@ -394,8 +394,8 @@ blsp1_uart2: serial@78b0000 {
                        clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
                                <&gcc GCC_BLSP1_AHB_CLK>;
                        clock-names = "core", "iface";
-                       dmas = <&blsp_dma 3>, <&blsp_dma 2>;
-                       dma-names = "rx", "tx";
+                       dmas = <&blsp_dma 2>, <&blsp_dma 3>;
+                       dma-names = "tx", "rx";
                };
 
                watchdog: watchdog@b017000 {