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(parent: ab65e04) | patch
clk: sunxi-ng: f1c100s: fix USB PHY gate bit offset
authorIcenowy Zheng <icenowy@aosc.io>
Thu, 14 Mar 2019 11:21:08 +0000 (19:21 +0800)
committerMaxime Ripard <maxime.ripard@bootlin.com>
Mon, 18 Mar 2019 07:07:21 +0000 (08:07 +0100)
commit6630aad719bc0a46dcc4a6732ab783c4c9b80f88
tree5dc7bad92780d824727d649d60222487c28b9096tree | snapshot
parentab65e04dc101d55f1509059725cf9d331141f6e8commit | diff
clk: sunxi-ng: f1c100s: fix USB PHY gate bit offset

The bit offset of the USB PHY clock gate on F1C100s should be 1, not 8.

Fix this problem.

Fixes: 0380126eb9af ("clk: sunxi-ng: add support for suniv F1C100s SoC")
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c diff | blob | history
https://github.com/torvalds/linux.git